This invention relates to a semiconductor integrated circuit device and a technique for fabrication thereof, particularly to a technique which is effective when applied to an interconnection-forming technique for a semiconductor circuit
As an interconnection forming process for a semiconductor integrated circuit, there is a process, for example, called a Damascene process. In this process, a buried interconnection is formed in an interconnection-forming groove by making an interconnection-forming groove in an insulating film, depositing an interconnection-forming conductor film all over the surface of the semiconductor substrate and then removing the conductor film at portions other than the groove by a chemical mechanical polishing method (CMP). This process is under investigation as a process for forming a buried interconnection composed of a copper base (copper or copper alloy) conductor material, on which it has been difficult to perform minute etching.
There also exists a Dual-Damascene process, which is an application of the above-described damascene process, in which a buried interconnection is formed in an interconnection-forming groove and a plug is formed in a connecting hole by making, in an insulating film, an interconnection-forming groove and a hole for connecting with a lower interconnection, depositing an interconnection-forming conductor film all over the surface of a semiconductor substrate and then removing the conductor film at portions other than the grooves by CMP. Particularly, in a semiconductor integrated circuit device having a multi-layered structure, the above process makes it possible to reduce the number of steps and, therefore, to decrease the interconnection cost.
The above-mentioned interconnection forming technique is described, for example, in Japanese Patent Application Laid-Open No. HEI 8-78410, xe2x80x9c1996 Symp. VLSI Tech. Digest pp.48-49xe2x80x9d, xe2x80x9cElectron materials, March issue, 22-27(1996)xe2x80x9d, Japanese Patent Application Laid-Open No. HEI 8-148560 or xe2x80x9cIBM. J. Res. Develop. Vol. 39(4), 419-435 (July, 1995)xe2x80x9d.
The present-inventors have found that the above-described technique for the formation of a buried interconnection has the following inherent problem.
More specifically, the problem is that no total image including the structure and fabrication has yet been established completely in the case where the technique for forming a buried interconnection is applied to a semiconductor integrated circuit device Particularly, in the dual damascene method, an interconnection-forming groove and connecting hole are buried with the same conductor film at the same time. Owing to the miniaturization of the interconnection or connecting hole, however, it becomes difficult to bury the connecting hole, which is more minute than the interconnection-forming groove, simultaneously with the interconnection-forming groove, while maintaining good electrical properties sufficiently. When copper is employed as a wiring material, it is difficult to bury copper in the connecting hole by the sputtering method. The plating method, on the other hand, has a higher burying capacity, but the crystal grains immediately after the film formation of copper are small, and so sufficient electrical properties are sometimes not available. In addition, the burying capacity of the plating method is not freely high, and the burying of a minute connecting hole having a high aspect ratio is difficult to achieve. Such a problem also appears when interconnection grooves with different aspect ratios exist in the same interconnection film to be buried.
An object of the present invention is therefore to provide, in a semiconductor integrated circuit device having a buried interconnection structure, a technique for favorably burying a conductor film for buried interconnection without using a highly-advanced technique.
Another object of the present invention is to provide, in a semiconductor integrated circuit device having a buried interconnection structure, a technique for promoting miniaturization of an interconnection groove and/or a connecting hole.
A further object of the present invention is to provide a technique for improving the reliability of a buried interconnection.
A still further object of the present invention is to provide a technique for introducing a copper-conductor material-buried interconnection in the whole structure of a semiconductor integrated circuit device without causing any inconvenience.
The above-described and other objects and novel features of the present invention will become apparent from the description herein and the accompanying drawings.
Among the features disclosed by the present application, typical ones will next be summarized briefly.
In one aspect of the present invention, there is provided a process for the fabrication of a semiconductor integrated circuit device having a buried interconnection over a semiconductor substrate, which comprises:
(a) making a connecting hole in an insulating film over said semiconductor substrate,
(b) forming, over said insulating film, a connecting conductor film to bury said connecting hole therewith,
(c) subjecting the thus-formed film to planarizing treatment after the formation of the connecting conductor film, thereby removing said conductor film at portions other than said connecting hole and forming a connecting conductor portion in said connecting hole,
(d) forming an interconnection groove in an interconnection forming region of said insulating film in which said connecting conductor portion has been formed,
(e) forming, on said insulating film, an interconnection conductor film to bury said interconnection groove therewith, and
(f) subjecting said interconnection conductor film to planarizing treatment after the formation of the interconnection conductor film, thereby removing said interconnection conductor film at portions other than the interconnection groove and forming a buried interconnection in said interconnection groove.
In another aspect of the present invention, there is also provided a process for the fabrication of a semiconductor integrated circuit device, which further comprises the step of thermal treatment subsequent to the planarizing treatment step of said interconnection conductor film, when said interconnection conductor film is made of copper or copper alloy and it has been formed by the sputtering method
In a further aspect of the present invention, there is also provided a process for the fabrication of a semiconductor integrated circuit having buried interconnection in plural interconnection layers disposed over a semiconductor substrate, wherein, upon formation of interconnection grooves of different size in the same buried interconnection layer, conductor films are buried in said interconnection grooves separately.
In a still further aspect of the present invention, there is also provided a process for the fabrication of a semiconductor integrated circuit device having a buried interconnection in an interconnection layer over a semiconductor substrate, comprising the steps of:
(a) making an interconnection groove and a connecting hole in an insulating film over said semiconductor substrate;
(b) forming, over said insulating film, a conductor film made of copper or copper alloy by the sputtering method so as to bury said interconnection groove and connecting hole with said conductor film;
(c) planarizing said conductor film made of copper or copper alloy to remove said conductor film at portions other than said interconnection groove and connecting hole, thereby burying said conductor film in said interconnection groove and connecting hole; and
(d) carrying out thermal treatment subsequent to the step of planarizing the conductor film made of copper or copper alloy.
In a still further aspect of the present invention, there is also provided a semiconductor integrated circuit device having a buried interconnection in an interconnection layer over a semiconductor substrate, wherein a portion at which said buried interconnection is brought into contact with said semiconductor substrate is composed of at least one wiring material selected from the group consisting of tungsten, tungsten alloy, titanium, titanium nitride, aluminum and aluminum alloy and said buried interconnection in the interconnection layer over the portion is composed of a copper base conductor material.
In a still further aspect of the present invention, there is also provided a semiconductor integrated circuit device having a buried interconnection in at least one interconnection layer over a semiconductor substrate, wherein an uppermost interconnection is made of aluminum or aluminum alloy and a lowest interconnection is made of copper or copper alloy.
In a still further aspect of the present invention, there is also provided a semiconductor integrated circuit device having a buried interconnection in interconnection layers over a semiconductor substrate, wherein an interconnection made of aluminum or aluminum alloy is connected with another interconnection made of copper or copper alloy, and a barrier conductor film is intersposed at a joint portion thereof.
In a still further aspect of the present invention, there is also provided a semiconductor integrated circuit device having a buried interconnection in plural interconnection layers over a semiconductor substrate, wherein upon electrical connection of interconnections over and under an interconnection layer of a predetermined embedded interconnection, a connecting conductor portion, which is disposed in a connecting hole extending from said upper interconnection toward said interconnection layer of a predetermined buried interconnection, and another connecting portion, which is disposed in a connecting hole extending from said lower interconnection toward said interconnection layer of a predetermined buried interconnection,are electrically connected through a connecting conductor portion for a relay which is disposed in a connecting groove of said interconnection layer of a predetermined buried interconnection; and said connecting conductor portion for relay is formed so that at least the length in the interconnection extending direction of a predetermined embedded interconnection is longer than the length of said connecting hole in said extending direction.